1. Field of the Invention
The present invention relates generally to an asynchronous transfer mode (ATM) switch.
2. Description of the Related Art
Generally in order to allow an ATM switch having a cell buffer to carry out a traffic control, e.g., a discard preference control function, a cell statistical information processing is carried out, and it is required to provide a cell counter for managing the number of cells stored in the buffer. Also in order to enable a contention control to realize fair transmission lines, generally in order to enable a flow control function, the cell statistical information processing is carried out, and the cell counter is used similar to the discard preference control function.
The traffic control must be carried out every output link, on which control traffic, such as the call/acceptance control (CAC) or congestion avoidance, may concentrate, so that the cell counter is provided in each of output links and each of classes. Therefore, the number of cell counters is large. This can not be avoided.
In order to generate flow control signals, the cell counter manages a threshold, so that the cell counter is provided with a threshold register. Since this threshold register sets the quality of service (QOS) and the cell discard preference (CLP) every output port, a large number of registers are provided. This can also be avoided.
In order to carry out the traffic control, the large number of cell counters themselves must frequently detect whether cells exist.
Conventionally, the cell counter is designed to be xe2x80x9cLxe2x80x9d, i.e., xe2x80x9c0xe2x80x9d, when it is reset.
Therefore, in conventional ATM switches a decoder 45 for detecting whether the bit value of all of corresponding cell counters 40 is xe2x80x9c0xe2x80x9d as shown in FIG. 6 must be provided in order to detect whether an ATM cell exists in each of cell buffers, so that there is a problem in that the ATM switch is large.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a compact ATM switch.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, an ATM switch comprises: a plurality of input line corresponding parts, each of which is provided in a corresponding one of input transmission lines, to which ATM cells are transmitted, each of the input line corresponding parts having a used quantity parameter control unit for monitoring the flow rate of the ATM cells, and a header converting part for converting VPI (Virtual Path Identifier) and VCI of a header of each of the ATM cells which have passed through the used quantity parameter control unit; a switch element having an input port part, which has a plurality of input ports, each of which corresponds to a corresponding one of the input line corresponding parts, and which receives the ATM cells transmitted from the input line corresponding parts via a corresponding one of the input ports, an output port part having a plurality of output ports, a self-routing switch for outputting the ATM cells, which are received via the input ports, from one of the output ports corresponding to the VPI and VCI of the header of each of the ATM cells, a first cell buffer for temporarily storing the ATM cells, and a first counter for counting the number of the ATM cells in the first cell buffer; and a plurality of output line corresponding parts provided so as to correspond to the output ports, each of the output line corresponding parts having a second cell buffer for temporarily storing the ATM cells transmitted from a corresponding one of the output ports and for outputting the ATM cells to a corresponding one of output transmission lines, and a second counter for counting the number of the ATM cells in the second cell buffer, wherein the used quantity parameter control unit has a third cell buffer for temporarily storing the ATM cells, and a third counter for counting the number of the ATM cells in the third cell buffer, and wherein each of bit values of at least one of the first through third counters is set to be xe2x80x9cHxe2x80x9d when the at least one of the first through third counters is preset.
The ATM switch may further comprise a decoder for determining whether the ATM cells exist in a corresponding one of the cell buffers, on the basis of the most significant value of the at least one of the first through third counters, each of the bit values of which is set to be xe2x80x9cHxe2x80x9d when the at least one of the first through third counters is preset.
The ATM switch may further comprise a control circuit for controlling the readout of the ATM cells from the second and third cell buffers.
The first cell buffer may be provided in the front stage of the self-routing switch so as to correspond to each of the input ports.
The first cell buffer may be provided in the subsequent stage of the self-routing switch so as to correspond to each of the output ports, and the first counter may be provided so as to correspond to each of the cell buffers.
The first cell buffer may be provided at each of cross points in the self-routing switch, and the first counter may be provided so as to correspond to each of the cell buffers.
The first cell buffer may be a common buffer.